The most straightforward approach to increasing data storage on a single-layer DRAM chip is to reduce the cell size.
However, the vertical capacitor in traditional DRAM designs creates very thick layers, making stacking difficult.
It’s important to note that 3D DRAM can refer to two distinct concepts.
One already in production is High-Bandwidth Memory (HBM).
However, HBM is a stacked-die memory, not a monolithic die like 3D NAND flash.
One approach to optimizing DRAM cells involves shrinking feature sizes through advanced lithography techniques.
This design employs a vertical-channel transistor and moves from the current 6F2 cell to 4F2.
However, it will require new materials, including ferroelectrics, and high precision to build.
Another promising direction involves laying the capacitor on its side to create thinner layers suitable for stacking.
“Etch and deposition experts may be shocked at what our simulations propose,” Vincent said.
Researchers are also exploring capacitor-less DRAM designs.
Neo Semiconductor has proposed a commercial technology using a floating-body cell with dual gating.
All current efforts will require many years of development and evaluation before they have commercial traction.
“New architectures are always more challenging than implementation of existing methodologies,” Soden said.
