The goal is to pave the way for designs packing billions or even trillions of transistors.
For the uninitiated, EDA stands for Electronic Design Automation.
It’s a set of software tools for designing electronic systems like integrated circuit chips.
Synopsys alsorevealedits physical verification and implementation solutions now support backside routing on TSMC’s A16 process.
A16 is TSMC’s most advanced process node ever,scheduledto be mass-produced in the second half of 2026.
This helps optimize power delivery and signal routing for better performance and density.
Synopsys adds that its tools have been cloud-certified by TSMC to further streamline the design process.
On the multi-die front, Synopsys' 3DIC Compiler platform has been enhanced through collaboration with Ansys and TSMC.
The company set 2030 as a target for 1.4nm A14 and 1nm A10 process nodes.
In parallel, it talked about developing advanced packaging technologies like CoWoS, InFO, and SoIC.
These technologies will together enable gargantuan multi-chiplet packages exceeding one trillion transistors around 2030.
With this new announcement, the chipmaker seems to be moving closer to its goal.
